Register maps

In this section the control and status register definitions of each gateware design in the dogma system are listed:

DOGMA_HUB1_DCM

The Dogma Controller Module is the central controller of the Dogma daq system. It distributes the 100MHz Dogma system clock and the trigger signals to all connected dogs (can also be subsequent hubs for higher fanout) and collects daq control signals (raw triggers from front-ends, trigger flow control). It also hosts the central trigger system (trigger priorisation, dead-time).

DOGMA_HUB1_DCM register map

ADDR

Name

Type

Function

0x00

BASIC_CTRL0

s/c
[0] general reset
[4] FPGA reload from flash
[8] clear statistics counters
[28] inject soft trigger to DCM

0x10

UID1

r/o

HW_UID[63:32]

0x11

UID0

r/o

HW_UID[31:0]

0x12

HW_INFO

r/o
[31:16] hardware module identifier
[15:0] gateware version identifier

0x13

COMPILE_TIME

r/o

32 bit unix timestamp from gateware compilation

0x14

TEMPERATURE

r/o
[23:16] die temperature
[11:0] temperature sensor value

0x18

TRG_ACC_CTR

r/o
counts up when trigger is accepted in DCM
[23:0] trigger number

0x19

TRG_REJ_CTR

r/o

DCM rejected physics trigger count (dead time)

0x1a

PULSER_TRG_REJ

r/o

DCM rejected PULSER trigger count (dead time)

0x1b

TRG_REJ_OVW

r/o

counter of incoming TRG_REJ signals from connected dogs

0x1c

DL_LINK_ESTABL

r/o

[29:0] Link established flags of downlinks to connected dogs

0x20

ADDR

r/w
[23:0] 24 bit unique dog address
(default value 0x000000 is ignored)

0x21

MC_ADDR

r/w

[23:0] 24 bit dog multicast address (default 0x00d810)

0x22

BIT_ADDR

r/w

[23:0] 24 bit dog bit address

0x23

RESERVED_GbE0

r/w

0x24

RESERVED_GbE1

r/w

0x25

RESERVED_GbE2

r/w

0x26

DL_TRG_IN_EN

r/w
enable incoming raw trigger signals from dogma downlinks
for injection to trigger system -> 1 bit per downlink

0x27

DEAD_TIME

r/w
set fixed trigger system dead time after trigger acceptance
t_d = VAL * 10ns

0x28

PULSER_EN

r/w

[0] internal trigger pulse generator enable

0x29

PULSER_PERIOD

r/w
[27:0] internal trigger pulse generator period
T_PULSER = VAL * 10ns

0x2a

PULSER_TRG_TYP

r/w
[3:0] trigger type to be sent when trigger from PULSER is accepted
0x1 = physics trigger, 0xd = calibration trigger

0x2b

MISC_CTRL

r/w

[0] disable LEDs

0x2c

DL_DISABLE

r/w

Seperately disable any downlink

0x2d

EXT_TRG_IN_EN

r/w
[0] enable trigger input on ADF J_LVDS pin pair PP0
[1] enable trigger input on ADR J_LVDS pin pair PP0

0x40

DL0_TRG_IN_CTR

r/o

Counter of incoming trigger requests from connected dog

0x60

DL0_TRG_REJ_CTR

r/o

Counter of incoming TRG_REJ signals from connected dog

DIRICH5d2_DEP

DIRICH5d2 Dogma End Point design with 32 channel TDC.

DIRICH5d2 dogma endpoint and TDC design register map

ADDR

Name

Type

Function

0x00

BASIC_CTRL0

s/c
[0] reset
[4] reload from flash (reboot)
[8] clear statistics counters
[9] reset dogma clock domain

0x10

UID1

r/o

HW_UID[63:32]

0x11

UID0

r/o

HW_UID[31:0]

0x12

HW_INFO

r/o
[31:16] hardware module identifier
[15:0] gateware version identifier

0x13

COMPILE_TIME

r/o

32 bit unix timestamp from gateware compilation

0x14

TEMPERATURE

r/o
[23:16] die temperature
[11:0] temperature sensor value

0x18

TRG_ACC_CTR

r/o

counts up when any trigger arrives on doglink

0x19

PHYS_TRG_CTR

r/o

count of accepted physics triggers

0x1a

CAL_TRG_CTR

r/o

count of accepted calibration triggers

0x1b

TRG_REJ_CTR

r/o

count of rejected triggers (readout not finished)

0x1c

DAQ_DEBUG

r/o
[19:16] daq fsm state
[11:0] daq payload fifo word count

0x1d

DOGLINK_STATUS

r/o
[29] doglink established
[28] recovered rxclk stable
[23:16] doglink init counter
[15:8] divclk align counter
[7:0] clock recovery toggle FF reset counter

0x1e

TRG_REQ_OUT_CTR

r/o

Counter for trigger requests generated from input signals

0x20

ADDR

r/w
[23:0] 24 bit unique dog address
(default value 0x000000 is ignored)

0x21

MC_ADDR

r/w

[23:0] 24 bit dog multicast address (default 0x00d5d2)

0x22

BIT_ADDR

r/w

[23:0] 24 bit dog bit address

0x23

RESERVED_GbE0

r/w

0x24

RESERVED_GbE1

r/w

0x25

RESERVED_GbE2

r/w

0x26

TRG_GEN_CH_EN

r/w
input enable map for trigger generation
(OR of all enabled inputs)
-> 1 bit per signal input

0x27

TRG_GEN_CH_INV

r/w
input invert map for trigger generation
-> 1 bit per signal input

0x28

TRG_GEN_MON_CTRL

r/w
0x0 = monitor asynchronous OR of enabled channels
0x1 = monitor synchronous captured trigger signal

0x29

DAQ_CTRL

r/w
[31] trigger handshake enable (TRG_ACK / TRG_RLS)
[8] enable event builder server/port load sharing
[5:4] number of LSBs from trigger number used to select target server
(allowed values are 0,1,2,3 -> 1/2/4/8 servers)
[2:0] number of LSBs from trigger number (after bits used for server)
used to select target port (allowed values are 0,1,2,3,4 -> 1/2/4/8/16
ports, target port = set port number + i)

0x2a

MISC_CTRL

r/w
[8] disable_leds
[3:0] test_line_sel: 0x0 = monitor trigger in, 0x1 = trg_gen_mon_out

0x40

INP_HIT_CTR_CH0

r/o
[31] input state bit
[30:0] TDC hit counter

0x80

TDC_CTRL

r/w
[8] TDC reset counters
[5] TDC light_mode_en

0x81

TDC_TRG_WIN

r/w
[31] trigger window enable
[26:16] post trigger window
[10:0] pre trigger window

0x82

TDC_CH_EN

r/w

TDC input enable (channels 1-32)

0x83

TDC_CH_INV

r/w

TDC input invert (channels 1-32)

0x84

TDC_HIT_FIFO_TH

r/w

[6:0] TDC hit buffer full threshold

0x85

DAQ_EVB_PORT

r/w

[15:0] DAQ event builder UDP port

0x86

DAQ_EVB0_MAC1

r/w

[31:0] DAQ event builder 0 MAC[63:32]

0x87

DAQ_EVB0_MAC0

r/w

[31:0] DAQ event builder 0 MAC[31:0]

0x88

DAQ_EVB0_IP

r/w

[31:0] DAQ event builder 0 IP[31:0]

0x89

DAQ_EVB1_MAC1

r/w

[31:0] DAQ event builder 1 MAC[63:32]

0x8a

DAQ_EVB1_MAC0

r/w

[31:0] DAQ event builder 1 MAC[31:0]

0x8b

DAQ_EVB1_IP

r/w

[31:0] DAQ event builder 1 IP[31:0]

0x8c

DAQ_EVB2_MAC1

r/w

[31:0] DAQ event builder 2 MAC[63:32]

0x8d

DAQ_EVB2_MAC0

r/w

[31:0] DAQ event builder 2 MAC[31:0]

0x8e

DAQ_EVB2_IP

r/w

[31:0] DAQ event builder 2 IP[31:0]

0x8f

DAQ_EVB3_MAC1

r/w

[31:0] DAQ event builder 3 MAC[63:32]

0x90

DAQ_EVB3_MAC0

r/w

[31:0] DAQ event builder 3 MAC[31:0]

0x91

DAQ_EVB3_IP

r/w

[31:0] DAQ event builder 3 IP[31:0]

0x92

DAQ_EVB4_MAC1

r/w

[31:0] DAQ event builder 4 MAC[63:32]

0x93

DAQ_EVB4_MAC0

r/w

[31:0] DAQ event builder 4 MAC[31:0]

0x94

DAQ_EVB4_IP

r/w

[31:0] DAQ event builder 4 IP[31:0]

0x95

DAQ_EVB5_MAC1

r/w

[31:0] DAQ event builder 5 MAC[63:32]

0x96

DAQ_EVB5_MAC0

r/w

[31:0] DAQ event builder 5 MAC[31:0]

0x97

DAQ_EVB5_IP

r/w

[31:0] DAQ event builder 5 IP[31:0]

0x98

DAQ_EVB6_MAC1

r/w

[31:0] DAQ event builder 6 MAC[63:32]

0x99

DAQ_EVB6_MAC0

r/w

[31:0] DAQ event builder 6 MAC[31:0]

0x9a

DAQ_EVB6_IP

r/w

[31:0] DAQ event builder 6 IP[31:0]

0x9b

DAQ_EVB7_MAC1

r/w

[31:0] DAQ event builder 7 MAC[63:32]

0x9c

DAQ_EVB7_MAC0

r/w

[31:0] DAQ event builder 7 MAC[31:0]

0x9d

DAQ_EVB7_IP

r/w

[31:0] DAQ event builder 7 IP[31:0]