The DOGMA - Introduction

The main dogma/paradigm of the DOGMA DAQ is to be able to separate the high-bandwidth data transport channel (which transports data from the front end electronics (FEEs) to the Eventbuilders) from the DAQ-specific clock/trigger/control channel as much as needed/ wanted. The second paradigm is to use a fully synchronous system, all driven by the Dogma Control Module (DCM). The DCM sends the dogma system clock, DAQ trigger signals (if wanted/needed by the user) and some low-level DAQ/system specific control commands via a serial link (in most cases an optical link, as this has the benefit to not be affected by GND-level shifts and issues like loops and thus facilitates a simpler power scheme) to all FEE-modules. Every trigger signal can be used for time synchronisation and pure time synchronisation triggers can be sent regularly as needed. This synchronisation assures that all devices in the system know (a short time after startup) what the absolute system time is (with different but deterministic latencies and with a fixed phase), which makes the reset/initialisation procedure of the full system and the re-synchronisation of a single device which had to be rebooted (e.g. due to single event upset) simple. (The data already sent until the re-synchronisation has finished, needs to be discarded in the eventbuilder).

The design principle is KISS, keep it small and simple. Therefore, it should be avoided as much as possible to re-invent and re-implement well known data transport mechanisms. Well tested and established protocols are preferred wherever possible.

All modules in the DOGMA system (dogs) are connected to the dogma controller module (DCM) through a tree-like network of (usually optical) serial point-to-point links. Only the DCM, the endpoints (dogs) and hubs are custom built. So every transmission originating from the DCM is broadcast to every dog (fan-out) and transmissions originating from dogs will be routed back to the DCM only (fan-in).

The serial links from the DCM towards the dogs (downstream) need special properties to be able to simultaneously transmit a clock that can be recovered with very low jitter (goal: < 10ps rms jitter) as well as trigger signals with deterministic timing/latency and moderate jitter compared to the actual time of the physical event (max 10ns). To be able to use optical links, the whole data on these links also needs to be dc-balanced.

In the other direction, from the dogs to the DCM (upstram), there is more freedom for the encoding of the data on the link because no clock needs to be transmitted. Of course, a dc-balanced encoding scheme is still necessary to be able to use optical links.

The design bit rate of the dog links is 800MBit/s which is the highest serial bit rate possible on the targeted lattice ECP5 devices since normal I/O pins need to be used (not the special high-speed transceivers) to be able to implement the special characteristics of the links.