Register maps

In this section the control and status register definitions of each gateware design in the dogma system are listed:

DOGMA_HUB1_DCM

The Dogma Controller Module is the central controller of the Dogma daq system. It distributes the 100MHz Dogma system clock and the trigger signals to all connected dogs (can also be subsequent hubs for higher fanout) and collects daq control signals (raw triggers from front-ends, trigger flow control). It also hosts the central trigger system (trigger priorisation, dead-time).

DOGMA_HUB1_DCM register map

ADDR	Name	Type	Function
0x00	SYS_RESET	s/c	[0] FPGA reload from flash (reboot) [4] FPGA reload from flash (reboot) [8] clear statistics counters [28] inject soft trigger to DCM
0x10	UID1	r/o	HW_UID[63:32]
0x11	UID0	r/o	HW_UID[31:0]
0x12	HW_INFO	r/o	32 bit gateware identifier [31:8] default dog multicast address
0x13	COMPILE_TIME	r/o	32 bit unix timestamp from gateware compilation
0x14	TEMPERATURE	r/o	[23:16] die temperature [11:0] temperature sensor value
0x18	SYSTEM_UPTIME	r/o	time since last reboot 33.554432ms per LSB
0x20	ADDR	r/w	[23:0] 24 bit unique dog address (default value 0x000000 is ignored)
0x21	MC_ADDR	r/w	[23:0] 24 bit dog multicast address (default 0xd81060)
0x22	RESERVED	r/w
0x23	RESERVED	r/w
0x24	MISC_CTRL	r/w	[0] disable LEDs
0x25	USR_SPI_DSBL_CS	r/w	[7:0] USR SPI chip select disables
0x26	PLL_CTRL	r/w	[2] pll force enable [1] pll reset [0] pll fallback mode
0x27	RESERVED	r/w
0x30000000	TRIG_ENABLE	r/w	[0] enable trigger system
0x30000001	DEAD_TIME	r/w	[15:0] dead time after trigger acceptance Td = VAL * 13.333ns
0x30000002	DL_TRIG_REQ_EN	r/w	Trigger request enable 1 bit per downlink
0x30000003	DL_DISABLE	r/w	Seperately disable any downlink
0x30000004	EXT_TRG_IN_EN	r/w	[0] enable trigger input on ADF J_LVDS pin pair PP0 [1] enable trigger input on ADR J_LVDS pin pair PP0
0x30000005	PULSER_EN	r/w	[0] internal trigger pulse generator enable
0x30000006	PULSER_PERIOD	r/w	[27:0] internal trigger pulse generator period T_PULSER = VAL * 13.333ns
0x30000007	PULSER_TRG_TYP	r/w	[3:0] trigger type to be sent when trigger from PULSER is accepted 0x1 = physics trigger, 0xd = calibration trigger
0x31000000	TRG_NUM_CTR	r/o	counts up when trigger is accepted in DCM [23:0] trigger number
0x31000001	DL_TRG_REJ_OVW	r/o	counter of incoming TRG_REJ signals from connected dogs
0x31000002	DL_LINK_ESTABL	r/o	[29:0] Link established flags of downlinks to connected dogs
0x31000003	TRG_REJ_CTR	r/o	DCM rejected physics trigger count (dead time)
0x31000004	DL0_TRG_IN_CTR	r/o	Counter of incoming trigger requests from connected dog
0x31000024	DL0_TRG_REJ_CTR	r/o	Counter of incoming TRG_REJ signals from connected dog

DIRICH5d2_DEP

DIRICH5d2 Dogma End Point design with 32 channel TDC.

DIRICH5d2 dogma endpoint and TDC design register map

ADDR	Name	Type	Function
0x00	SYS_RESET	s/c	[0] FPGA reload from flash (reboot) [8] clear statistics counters
0x10	UID1	r/o	HW_UID[63:32]
0x11	UID0	r/o	HW_UID[31:0]
0x12	HW_INFO	r/o	[31:16] hardware module identifier [15:0] gateware version identifier
0x13	COMPILE_TIME	r/o	32 bit unix timestamp from gateware compilation
0x14	TEMPERATURE	r/o	[23:16] die temperature [11:0] temperature sensor value
0x18	SYSTEM_UPTIME	r/o	time since last reboot 33.554432ms per LSB
0x20	ADDR	r/w	[23:0] 24 bit unique dog address (default value 0x000000 is ignored)
0x21	MC_ADDR	r/w	[23:0] 24 bit dog multicast address
0x24	LEDS_CTRL	r/w	[0] Disable LEDs | [1] Party mode
0x25	USR_SPI_DSBL_CS	r/w	[7:0] Disable CS signal activity per SPI channel
0x26	PLL_CTRL	r/w	[2] pll reset [1] pll force enable [0] pll fallback mode
0x10000000	PERIPH_SPI	r/w	SPI base address
0x10000400	PERIPH_I2C	r/w	I2C base address
0x10000800	PERIPH_USPI	r/w	User SPI base address
0x20000000	ETH_MAC0	r/o	Device MAC (MSBs)
0x20000001	ETH_MAC1	r/o	Device MAC (LSBs)
0x20000002	ETH_IP	r/o	Actual IP address
0x20000003	ETH_SUBNETMASK	r/o	Actual subnet mask
0x20000010	ETH_STATIC_IP	r/w	Static IP address
0x20000011	ETH_STATIC_SUBNETMASK	r/w	Static subnet mask
0x20000020	ETH_MULTICAST0	r/w	Device multicast address 0
0x20000021	ETH_MULTICAST1	r/w	Device multicast address 1
0x20000022	ETH_MULTICAST2	r/w	Device multicast address 2
0x20000023	ETH_MULTICAST3	r/w	Device multicast address 3
0x20000024	ETH_MULTICAST4	r/w	Device multicast address 4
0x20000025	ETH_MULTICAST5	r/w	Device multicast address 5
0x20000026	ETH_MULTICAST6	r/w	Device multicast address 6
0x20000027	ETH_MULTICAST7	r/w	Device multicast address 7
0x30000000	DL_VERSION	r/o	Version number of Doglink
0x30000001	DL_STATUS	r/o	[0] RX active (received first dogtime; 4th step) [1] RX established (found sync between clock and data; 3rd step) [2] TX active (all PLLs locked; 2nd step) [3] RX clock recovered (1st step)
0x30000010	DL_UPTIME	r/o	time since dogma uplink was established 33.554432ms per LSB
0x30000011	DL_RX_CTR	r/o	Counts up when any trigger arrives on doglink
0x30000012	DL_TX_CTR	r/o	Counts up when any trigger is sent on doglink
0x30000013	DL_SYNC_CTR	r/o	Counts up when the doglink resyncs (should only happen once in a sane system)
0x30000100	DL_TRIG_REJ	r/o	Counts up when a trigger gets rejected
0x30000101	DL_TRIG_FIFOCNT	r/o	Number of entries in trigger fifo (current maximum is 4)
0x40000000	UR_VERSION	r/o	Unified Readout version
0x40000001	UR_NUM_CHANNELS	r/o	Number of readout channels
0x40000010	UR_CH_DIS0	r/w	Input disable channels 1-32
0x40000011	UR_CH_DIS1	r/w	Input disable channels 33-64
0x40000012	UR_CH_DIS2	r/w	Input disable channels 65-96
0x40000013	UR_CH_DIS3	r/w	Input disable channels 97-128
0x40000014	UR_CH_INV0	r/w	Input invert channels 1-32
0x40000015	UR_CH_INV1	r/w	Input invert channels 33-64
0x40000016	UR_CH_INV2	r/w	Input invert channels 65-96
0x40000017	UR_CH_INV3	r/w	Input invert channels 97-128
0x40000018	UR_TRIG_WIN_PRE	r/w	[18:0] Trigger window pre (LHS of interval). 150 MHz
0x40000019	UR_TRIG_WIN_POST	r/w	[18:0] Trigger window post (RHS of interval). 150 MHz
0x4000001a	UR_RESET_COUNTERS	r/w	Reset counters
0x40100000	UR_HIT_CTR_CH0	r/o	[27] UR input state bit [26:0] UR hit counter
0x40101000	UR_LOST_HIT_CTR_CH0	r/o	Lost hit counter
0x41000000	UR_EVB_CTRL	r/w	[8] enable event builder server/port load sharing [5:4] number of LSBs from trigger number used to select target server (allowed values are 0,1,2,3 -> 1/2/4/8 servers) [2:0] number of LSBs from trigger number (after bits used for server) used to select target port (allowed values are 0,1,2,3,4 -> 1/2/4/8/16 ports, target port = set port number + i)
0x41000001	UR_EVB_PORT	r/w	[15:0] DAQ event builder UDP port
0x41000100	UR_EVB0_IP	r/w	DAQ event builder 0 IP
0x41000101	UR_EVB1_IP	r/w	DAQ event builder 1 IP
0x41000102	UR_EVB2_IP	r/w	DAQ event builder 2 IP
0x41000103	UR_EVB3_IP	r/w	DAQ event builder 3 IP
0x41000104	UR_EVB4_IP	r/w	DAQ event builder 4 IP
0x41000105	UR_EVB5_IP	r/w	DAQ event builder 5 IP
0x41000106	UR_EVB6_IP	r/w	DAQ event builder 6 IP
0x41000107	UR_EVB7_IP	r/w	DAQ event builder 7 IP
0x41000200	UR_EVB0_MAC1	r/w	[15:0] DAQ event bilder 0 MAC[47:32]
0x41000201	UR_EVB0_MAC0	r/w	DAQ event bilder 0 MAC[31:0]
0x41000202	UR_EVB1_MAC1	r/w	[15:0] DAQ event bilder 1 MAC[47:32]
0x41000203	UR_EVB1_MAC0	r/w	DAQ event bilder 1 MAC[31:0]
0x41000204	UR_EVB2_MAC1	r/w	[15:0] DAQ event bilder 2 MAC[47:32]
0x41000205	UR_EVB2_MAC0	r/w	DAQ event bilder 2 MAC[31:0]
0x41000206	UR_EVB3_MAC1	r/w	[15:0] DAQ event bilder 3 MAC[47:32]
0x41000207	UR_EVB3_MAC0	r/w	DAQ event bilder 3 MAC[31:0]
0x41000208	UR_EVB4_MAC1	r/w	[15:0] DAQ event bilder 4 MAC[47:32]
0x41000209	UR_EVB4_MAC0	r/w	DAQ event bilder 4 MAC[31:0]
0x4100020a	UR_EVB5_MAC1	r/w	[15:0] DAQ event bilder 5 MAC[47:32]
0x4100020b	UR_EVB5_MAC0	r/w	DAQ event bilder 5 MAC[31:0]
0x4100020c	UR_EVB6_MAC1	r/w	[15:0] DAQ event bilder 6 MAC[47:32]
0x4100020d	UR_EVB6_MAC0	r/w	DAQ event bilder 6 MAC[31:0]
0x4100020e	UR_EVB7_MAC1	r/w	[15:0] DAQ event bilder 7 MAC[47:32]
0x4100020f	UR_EVB7_MAC0	r/w	DAQ event bilder 7 MAC[31:0]
0x41000300	UR_EVT_DROP_CTR	r/0	Dropped events due to overflow of fifo
0x50000000	TRGGEN_CTR	r/o	Number of sent trigger requests
0x50000800	TRGGEN_EN_MAP	r/w	Enable map for channels 0-31

BLACKCAT_DEP

Several BLACKCAT compatible devices.

Blackcat dogma endpoint register map

ADDR	Name	Type	Function
0x00	SYS_RESET	s/c	[31] FPGA reload from flash [30] snapshot RX/TX frame counters [29] snapshot DLM counters [28] snapshot protocol counters [27] snapshot IP/MAC settings [5] stop DLM surveillance [4] start DLM surveillance [1] warm reset [0] cold reset
0x01	SYS_GBE_FC	s/c	[31:28] PCSD select, bit coded [27:24] PCSC select, bitcoded [23:20] PCSB select, bitcoded [19:16] PCSA select, bitcoded [15:0] GbE FlowControl Pause value
0x02	SYS_DLM_FUNC	s/c	[30] DLM push start [29] SCC FIFO reset [28] phase measurement channel write [21] store reset DLM value (only for Mainz systems) [20] store trigger DLM value (only for Mainz systems) [18] TRG write (not in P-ONE systems) [17] SCC start (not in P-ONE systems) [16] SCC data write (not in P-ONE systems) [7:0] SCC/TRG data (not in P-ONE systems)
0x10	SYS_STAT_UIDH	r/o	UID MSB of board
0x11	SYS_STAT_UIDL	r/o	UID LSB of board
0x12	SYS_STAT_HWGW	r/o	[21:20] hardware type [19:16] origin [15:0] gateware type
0x13	SYS_STAT_COMPILATION	r/o	compilation date
0x14	SYS_STAT_TEMPERATURE	r/o	[23:16] die temperature (only ECP5) [11:0] temperature sensor
0x15	SYS_STAT_FEATURES	r/o	[31:28] number of additional status registers [5] UART included [4] FWDB included [3] FWDA included [2] DOGMA included [1] PING included [0] DHCP included
0x16	SYS_ACFG_OFFSET	r/o	[23:0] autoconfig ROM offset
0x17	SYS_ACFG_LENGTH	r/o	[23:0] autoconfig ROM length
0x18	SYS_STAT_BOARD”	r/o	[31] clock select status [30] flash select line (only TOMcat) [29] I2C bus locked (only TOMcat) [27] PLL (local 10MHZ) locked [26] PLL (onboard 125MHz) locked [25] PLL (internal 250MHz) locked [20] DLMs locked (surveillance) [19] AD9546 PLL locked (only TOMcat) [18] DLMs synced to IRIG-B [16] ROOT module [15:0] uplink establishment counter
0x20	SYS_CTRL_ADDR_UNI	r/w	[23:0] unicast DOGMA address
0x21	SYS_CTRL_ADDR_MULTI	r/w	[23:0] multicast DOGMA address (0xfd)
0x22	SYS_CTRL_ADDR_BIT	r/w	[23:0] bitcast DOGMA address (0xfe)
0x23	SYS_CTRL_FIXED_IP	r/w	fixed IP address (no DHCP active)
0x24	SYS_CTRL_SETUP	r/w	[31] DHCP disable [30] LEDs offset [29] 200MHz oscillator on (only TOMcat) [28] debug GPIO enable [27] FlashROM select (normal/GoldenImage, only TOMcat) [26] disable FPGA I2C access (only TOMcat) [25] auxiliary SFP0 on (only P-ONE backplane) [24] auxiliary SFP1 on (only P-ONE backplane) [20] disable IRIG-B data stream (only P-ONE master) [16] timing test select (only TOMcat) [15:0] timeout for IO control buffer full
0x25	SYS_CTRL_MTU	r/w	[31:16] MTU (MAC level for frame handling) [15:0] payload size for GbE core frames
0x40	MST_SLV_LIST	r/o	[31:16] master port list (bit coded) [15:0] slave port list (bit coded)
0x41	LAM_ACT_LIST	r/o	[31:16] LAM port list (bit coded) [15:0] active port list (bit coded)
0x42	RX_FRAME_COUNTERS	r/o	[31:28] SerDes channel (A0 = 0, B0 = 4, …) [27:0] RX frame counters (check docu for decoding)
0x43	DLM_COUNTERS	r/o	[31:28] SerDes channel (A0 =, B0 = 4, …) [27:0] DLM counters (check docu for decoding)
0x44	PROTOCOL_COUNTERS	r/o	[31:28] protocol number [27:0] protocol based counters (check docu for decoding)