Register maps

In this section the control and status register definitions of each gateware design in the dogma system are listed:

DOGMA_HUB1_DCM

The Dogma Controller Module is the central controller of the Dogma daq system. It distributes the 100MHz Dogma system clock and the trigger signals to all connected dogs (can also be subsequent hubs for higher fanout) and collects daq control signals (raw triggers from front-ends, trigger flow control). It also hosts the central trigger system (trigger priorisation, dead-time).

DOGMA_HUB1_DCM register map

ADDR

Name

Type

Function

0x00

SYS_RESET

s/c
[0] FPGA reload from flash (reboot)
[4] FPGA reload from flash (reboot)
[8] clear statistics counters
[28] inject soft trigger to DCM

0x10

UID1

r/o

HW_UID[63:32]

0x11

UID0

r/o

HW_UID[31:0]

0x12

HW_INFO

r/o
[31:16] hardware module identifier
[15:0] gateware version identifier

0x13

COMPILE_TIME

r/o

32 bit unix timestamp from gateware compilation

0x14

TEMPERATURE

r/o
[23:16] die temperature
[11:0] temperature sensor value

0x18

SYSTEM_UPTIME

r/o
time since last reboot
33.554432ms per LSB

0x1b

TRG_ACC_CTR

r/o
counts up when trigger is accepted in DCM
[23:0] trigger number

0x1c

TRG_REJ_OVW

r/o

counter of incoming TRG_REJ signals from connected dogs

0x1d

DL_LINK_ESTABL

r/o

[29:0] Link established flags of downlinks to connected dogs

0x1e

TRG_REJ_CTR

r/o

DCM rejected physics trigger count (dead time)

0x20

ADDR

r/w
[23:0] 24 bit unique dog address
(default value 0x000000 is ignored)

0x21

MC_ADDR

r/w

[23:0] 24 bit dog multicast address (default 0x00d810)

0x22

BIT_ADDR

r/w

[23:0] 24 bit dog bit address

0x23

RESERVED_GbE0

r/w

0x24

RESERVED_GbE1

r/w

0x25

TRIG_ENABLE

r/w

[0] enable DCM trigger module

0x26

DL_TRG_IN_EN

r/w
enable incoming raw trigger signals from dogma downlinks
for injection to trigger system -> 1 bit per downlink

0x27

DEAD_TIME

r/w
set fixed trigger system dead time after trigger acceptance
t_d = VAL * 10ns

0x28

PULSER_EN

r/w

[0] internal trigger pulse generator enable

0x29

PULSER_PERIOD

r/w
[27:0] internal trigger pulse generator period
T_PULSER = VAL * 10ns

0x2a

PULSER_TRG_TYP

r/w
[3:0] trigger type to be sent when trigger from PULSER is accepted
0x1 = physics trigger, 0xd = calibration trigger

0x2b

MISC_CTRL

r/w

[0] disable LEDs

0x2c

DL_DISABLE

r/w

Seperately disable any downlink

0x2d

EXT_TRG_IN_EN

r/w
[0] enable trigger input on ADF J_LVDS pin pair PP0
[1] enable trigger input on ADR J_LVDS pin pair PP0

0x40

DL0_TRG_IN_CTR

r/o

Counter of incoming trigger requests from connected dog

0x60

DL0_TRG_REJ_CTR

r/o

Counter of incoming TRG_REJ signals from connected dog

DIRICH5d2_DEP

DIRICH5d2 Dogma End Point design with 32 channel TDC.

DIRICH5d2 dogma endpoint and TDC design register map

ADDR

Name

Type

Function

0x00

SYS_RESET

s/c
[0] FPGA reload from flash (reboot)
[8] clear statistics counters

0x10

UID1

r/o

HW_UID[63:32]

0x11

UID0

r/o

HW_UID[31:0]

0x12

HW_INFO

r/o
[31:16] hardware module identifier
[15:0] gateware version identifier

0x13

COMPILE_TIME

r/o

32 bit unix timestamp from gateware compilation

0x14

TEMPERATURE

r/o
[23:16] die temperature
[11:0] temperature sensor value

0x18

SYSTEM_UPTIME

r/o
time since last reboot
33.554432ms per LSB

0x19

DOGLINK_UPTIME

r/o
time since dogma uplink was established
33.554432ms per LSB

0x1a

DOGLINK_STATUS

r/o
[29] doglink established
[28] recovered rxclk stable
[23:16] dogtime sync counter
[15:8] doglink init counter
[7:0] clock recovery toggle FF reset counter

0x1b

TRG_CTR

r/o

counts up when any trigger arrives on doglink

0x1c

TRG_REJ_CTR

r/o

count of rejected triggers (readout not finished)

0x1d

DATA_LOSS_CTR

r/o

count of lost TDC data words

0x1e

TRG_REQ_OUT_CTR

r/o

Counter for trigger requests generated from input signals

0x20

ADDR

r/w
[23:0] 24 bit unique dog address
(default value 0x000000 is ignored)

0x21

MC_ADDR

r/w

[23:0] 24 bit dog multicast address (default 0x00d5d2)

0x22

BIT_ADDR

r/w

[23:0] 24 bit dog bit address

0x23

RESERVED_GbE0

r/w

0x24

RESERVED_GbE1

r/w

0x25

RESERVED_GbE2

r/w

0x26

TRG_GEN_CH_EN

r/w
input enable map for trigger generation
-> 1 bit per signal input

0x27

MISC_CTRL

r/w
[31] external PLL force enable
[30] external PLL reset
[29] external PLL fallback mode enable
[28] select clock path through external PLL
[24] disable_leds
[23:20] monitor select (currently don’t care)
[17]* test_line_sel: 0 = normal tdc hit inputs, 1 = tdc hits fed from test line input
[16]* mute TDC external hit inputs
[15:0] trig_gen_ctrl (to be documented)
* only valid in PIGGY_LVDSIN1 design

0x28

DAQ_CTRL

r/w
[31] trigger handshake enable (TRG_ACK / TRG_RLS)
[12] enable DAQ/ trigger acceptance (set event builder info first!)
[8] enable event builder server/port load sharing
[5:4] number of LSBs from trigger number used to select target server
(allowed values are 0,1,2,3 -> 1/2/4/8 servers)
[2:0] number of LSBs from trigger number (after bits used for server)
used to select target port (allowed values are 0,1,2,3,4 -> 1/2/4/8/16
ports, target port = set port number + i)

0x29

TDC_HIT_IN_SEL

r/w
Only existing in newest “any_in” design
[2] enable test_line input to TDC
[1] enable PIGGY inputs to TDC
[0] enable AMP inputs to TDC (default)

0x40

INP_HIT_CTR_CH0

r/o
[31] input state bit
[30:0] TDC hit counter

0x80

TDC_CTRL

r/w
[8] TDC reset counters
[5] TDC light_mode_en

0x81

TDC_TRG_WIN

r/w
[31] trigger window enable
[26:16] post trigger window
[10:0] pre trigger window

0x82

TDC_CH_EN

r/w

TDC input enable (channels 1-32)

0x83

TDC_CH_INV

r/w

TDC input invert (channels 1-32)

0x84

TDC_HIT_FIFO_TH

r/w

[6:0] TDC hit buffer full threshold

0x85

DAQ_EVB_PORT

r/w

[15:0] DAQ event builder UDP port

0x86

DAQ_EVB0_MAC1

r/w

[31:0] DAQ event builder 0 MAC[63:32]

0x87

DAQ_EVB0_MAC0

r/w

[31:0] DAQ event builder 0 MAC[31:0]

0x88

DAQ_EVB0_IP

r/w

[31:0] DAQ event builder 0 IP[31:0]

0x89

DAQ_EVB1_MAC1

r/w

[31:0] DAQ event builder 1 MAC[63:32]

0x8a

DAQ_EVB1_MAC0

r/w

[31:0] DAQ event builder 1 MAC[31:0]

0x8b

DAQ_EVB1_IP

r/w

[31:0] DAQ event builder 1 IP[31:0]

0x8c

DAQ_EVB2_MAC1

r/w

[31:0] DAQ event builder 2 MAC[63:32]

0x8d

DAQ_EVB2_MAC0

r/w

[31:0] DAQ event builder 2 MAC[31:0]

0x8e

DAQ_EVB2_IP

r/w

[31:0] DAQ event builder 2 IP[31:0]

0x8f

DAQ_EVB3_MAC1

r/w

[31:0] DAQ event builder 3 MAC[63:32]

0x90

DAQ_EVB3_MAC0

r/w

[31:0] DAQ event builder 3 MAC[31:0]

0x91

DAQ_EVB3_IP

r/w

[31:0] DAQ event builder 3 IP[31:0]

0x92

DAQ_EVB4_MAC1

r/w

[31:0] DAQ event builder 4 MAC[63:32]

0x93

DAQ_EVB4_MAC0

r/w

[31:0] DAQ event builder 4 MAC[31:0]

0x94

DAQ_EVB4_IP

r/w

[31:0] DAQ event builder 4 IP[31:0]

0x95

DAQ_EVB5_MAC1

r/w

[31:0] DAQ event builder 5 MAC[63:32]

0x96

DAQ_EVB5_MAC0

r/w

[31:0] DAQ event builder 5 MAC[31:0]

0x97

DAQ_EVB5_IP

r/w

[31:0] DAQ event builder 5 IP[31:0]

0x98

DAQ_EVB6_MAC1

r/w

[31:0] DAQ event builder 6 MAC[63:32]

0x99

DAQ_EVB6_MAC0

r/w

[31:0] DAQ event builder 6 MAC[31:0]

0x9a

DAQ_EVB6_IP

r/w

[31:0] DAQ event builder 6 IP[31:0]

0x9b

DAQ_EVB7_MAC1

r/w

[31:0] DAQ event builder 7 MAC[63:32]

0x9c

DAQ_EVB7_MAC0

r/w

[31:0] DAQ event builder 7 MAC[31:0]

0x9d

DAQ_EVB7_IP

r/w

[31:0] DAQ event builder 7 IP[31:0]

0x4000

UR_VERSION

r/o

Unified Readout version

0x4001

UR_NUM_CHANNELS

r/o

Number of readout channels

0x4010

UR_CH_DIS0

r/w

Input disable channels 1-32

0x4011

UR_CH_DIS1

r/w

Input disable channels 33-64

0x4012

UR_CH_DIS2

r/w

Input disable channels 65-96

0x4013

UR_CH_DIS3

r/w

Input disable channels 97-128

0x4014

UR_CH_INV0

r/w

Input invert channels 1-32

0x4015

UR_CH_INV1

r/w

Input invert channels 33-64

0x4016

UR_CH_INV2

r/w

Input invert channels 65-96

0x4017

UR_CH_INV3

r/w

Input invert channels 97-128

0x4018

UR_TRIG_WIN_PRE

r/w

[18:0] Trigger window pre (LHS of interval). 150 MHz

0x4019

UR_TRIG_WIN_POST

r/w

[18:0] Trigger window post (RHS of interval). 150 MHz

0x401a

UR_RESET_COUNTERS

r/w

Reset counters

0x4100

UR_HIT_CTR_CH0

r/o
[27] UR input state bit
[26:0] UR hit counter

0x4180

UR_LOST_HIT_CTR_CH0

r/o

Lost hit counter

0x5000

LB_CTRL

r/w
[8] enable event builder server/port load sharing
[5:4] number of LSBs from trigger number used to select target server
(allowed values are 0,1,2,3 -> 1/2/4/8 servers)
[2:0] number of LSBs from trigger number (after bits used for server)
used to select target port (allowed values are 0,1,2,3,4 -> 1/2/4/8/16
ports, target port = set port number + i)

0x5001

LB_EVB_PORT

r/w

[15:0] DAQ event builder UDP port

0x5100

LB_EVB0_IP

r/w

DAQ event builder 0 IP

0x5101

LB_EVB1_IP

r/w

DAQ event builder 1 IP

0x5102

LB_EVB2_IP

r/w

DAQ event builder 2 IP

0x5103

LB_EVB3_IP

r/w

DAQ event builder 3 IP

0x5104

LB_EVB4_IP

r/w

DAQ event builder 4 IP

0x5105

LB_EVB5_IP

r/w

DAQ event builder 5 IP

0x5106

LB_EVB6_IP

r/w

DAQ event builder 6 IP

0x5107

LB_EVB7_IP

r/w

DAQ event builder 7 IP

0x5200

LB_EVB0_MAC1

r/w

[15:0] DAQ event bilder 0 MAC[47:32]

0x5300

LB_EVB0_MAC0

r/w

DAQ event bilder 0 MAC[31:0]

0x5201

LB_EVB1_MAC1

r/w

[15:0] DAQ event bilder 1 MAC[47:32]

0x5301

LB_EVB1_MAC0

r/w

DAQ event bilder 1 MAC[31:0]

0x5202

LB_EVB2_MAC1

r/w

[15:0] DAQ event bilder 2 MAC[47:32]

0x5302

LB_EVB2_MAC0

r/w

DAQ event bilder 2 MAC[31:0]

0x5203

LB_EVB3_MAC1

r/w

[15:0] DAQ event bilder 3 MAC[47:32]

0x5303

LB_EVB3_MAC0

r/w

DAQ event bilder 3 MAC[31:0]

0x5204

LB_EVB4_MAC1

r/w

[15:0] DAQ event bilder 4 MAC[47:32]

0x5304

LB_EVB4_MAC0

r/w

DAQ event bilder 4 MAC[31:0]

0x5205

LB_EVB5_MAC1

r/w

[15:0] DAQ event bilder 5 MAC[47:32]

0x5305

LB_EVB5_MAC0

r/w

DAQ event bilder 5 MAC[31:0]

0x5206

LB_EVB6_MAC1

r/w

[15:0] DAQ event bilder 6 MAC[47:32]

0x5306

LB_EVB6_MAC0

r/w

DAQ event bilder 6 MAC[31:0]

0x5207

LB_EVB7_MAC1

r/w

[15:0] DAQ event bilder 7 MAC[47:32]

0x5307

LB_EVB7_MAC0

r/w

DAQ event bilder 7 MAC[31:0]

BLACKCAT_DEP

Several BLACKCAT compatible devices.

Blackcat dogma endpoint register map

ADDR

Name

Type

Function

0x00

SYS_RESET

s/c
[31] FPGA reload from flash
[30] snapshot RX/TX frame counters
[29] snapshot DLM counters
[28] snapshot protocol counters
[27] snapshot IP/MAC settings
[5] stop DLM surveillance
[4] start DLM surveillance
[1] warm reset
[0] cold reset

0x01

SYS_GBE_FC

s/c
[31:28] PCSD select, bit coded
[27:24] PCSC select, bitcoded
[23:20] PCSB select, bitcoded
[19:16] PCSA select, bitcoded
[15:0] GbE FlowControl Pause value

0x02

SYS_DLM_FUNC

s/c
[30] DLM push start
[29] SCC FIFO reset
[28] phase measurement channel write
[21] store reset DLM value (only for Mainz systems)
[20] store trigger DLM value (only for Mainz systems)
[18] TRG write (not in P-ONE systems)
[17] SCC start (not in P-ONE systems)
[16] SCC data write (not in P-ONE systems)
[7:0] SCC/TRG data (not in P-ONE systems)

0x10

SYS_STAT_UIDH

r/o

UID MSB of board

0x11

SYS_STAT_UIDL

r/o

UID LSB of board

0x12

SYS_STAT_HWGW

r/o
[21:20] hardware type
[19:16] origin
[15:0] gateware type

0x13

SYS_STAT_COMPILATION

r/o

compilation date

0x14

SYS_STAT_TEMPERATURE

r/o
[23:16] die temperature (only ECP5)
[11:0] temperature sensor

0x15

SYS_STAT_FEATURES

r/o
[31:28] number of additional status registers
[5] UART included
[4] FWDB included
[3] FWDA included
[2] DOGMA included
[1] PING included
[0] DHCP included

0x16

SYS_ACFG_OFFSET

r/o

[23:0] autoconfig ROM offset

0x17

SYS_ACFG_LENGTH

r/o

[23:0] autoconfig ROM length

0x18

SYS_STAT_BOARD”

r/o
[31] clock select status
[30] flash select line (only TOMcat)
[29] I2C bus locked (only TOMcat)
[27] PLL (local 10MHZ) locked
[26] PLL (onboard 125MHz) locked
[25] PLL (internal 250MHz) locked
[20] DLMs locked (surveillance)
[19] AD9546 PLL locked (only TOMcat)
[18] DLMs synced to IRIG-B
[16] ROOT module
[15:0] uplink establishment counter

0x20

SYS_CTRL_ADDR_UNI

r/w

[23:0] unicast DOGMA address

0x21

SYS_CTRL_ADDR_MULTI

r/w

[23:0] multicast DOGMA address (0xfd)

0x22

SYS_CTRL_ADDR_BIT

r/w

[23:0] bitcast DOGMA address (0xfe)

0x23

SYS_CTRL_FIXED_IP

r/w

fixed IP address (no DHCP active)

0x24

SYS_CTRL_SETUP

r/w
[31] DHCP disable
[30] LEDs offset
[29] 200MHz oscillator on (only TOMcat)
[28] debug GPIO enable
[27] FlashROM select (normal/GoldenImage, only TOMcat)
[26] disable FPGA I2C access (only TOMcat)
[25] auxiliary SFP0 on (only P-ONE backplane)
[24] auxiliary SFP1 on (only P-ONE backplane)
[20] disable IRIG-B data stream (only P-ONE master)
[16] timing test select (only TOMcat)
[15:0] timeout for IO control buffer full

0x25

SYS_CTRL_MTU

r/w
[31:16] MTU (MAC level for frame handling)
[15:0] payload size for GbE core frames

0x40

MST_SLV_LIST

r/o
[31:16] master port list (bit coded)
[15:0] slave port list (bit coded)

0x41

LAM_ACT_LIST

r/o
[31:16] LAM port list (bit coded)
[15:0] active port list (bit coded)

0x42

RX_FRAME_COUNTERS

r/o
[31:28] SerDes channel (A0 = 0, B0 = 4, …)
[27:0] RX frame counters (check docu for decoding)

0x43

DLM_COUNTERS

r/o
[31:28] SerDes channel (A0 =, B0 = 4, …)
[27:0] DLM counters (check docu for decoding)

0x44

PROTOCOL_COUNTERS

r/o
[31:28] protocol number
[27:0] protocol based counters (check docu for decoding)