Register maps
==========================

In this section the control and status register definitions of each gateware
design in the dogma system are listed:


DOGMA_HUB1_DCM
----------------------------------

The **D**\ ogma **C**\ ontroller **M**\ odule is the central controller of the
Dogma daq system. It distributes the 100MHz Dogma system clock and the trigger
signals to all connected dogs (can also be subsequent hubs for higher fanout)
and collects daq control signals (raw triggers from front-ends,  trigger flow
control). It also hosts the central trigger system (trigger priorisation,
dead-time).

.. csv-table:: DOGMA_HUB1_DCM register map
   :file: ../../src/dogma/data/dogma_hub1_dcm.csv
   :widths: 10, 10, 20, 60
   :header-rows: 1


DIRICH5d2_DEP
----------------------------------

DIRICH5d2 **D**\ ogma **E**\ nd **P**\ oint design with 32 channel TDC.

.. csv-table:: DIRICH5d2 dogma endpoint and TDC design register map
   :file: ../../src/dogma/data/dirich5d2_dep.csv
   :widths: 10, 10, 20, 60
   :header-rows: 1